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apds-9120 integrated optical proximity sensors data sheet description avagos apds-9120 is an integrated optical proximity sensor that combines built-in signal conditioning and space-saving packaging technology. this integrated sensor provides ease of use, as it elimi- nates design e?orts required in implementing external led drivers, signal ?ltering and ampli?cation, sunlight and ambient light immunity and led stuck high protec- tion circuit. apds-9120 is designed to be a robust proximity sensor. it has arti?cial light immunity and operates in sunlight exposure. both analog and/or digital output options are available. to maximize power savings and battery life in applications such as portable or battery-operated devices, apds-9120 has a shutdown mode feature. with an external limiting resistor, the led current of the optical proximity sensors can be con?gured to various levels. the pulse width, burst rate, duty cycle and frequency can be controlled to minimize power consumption. these features make it ideal for low power mobile and handheld devices. application support information the application engineering group is available to assist you with the application design associated with apds- 9120 module. you can contact them through your local sales representatives for additional details. features small form factor with conditioning ic, emitter and detector integrated into one single package C h1.1mm x w4.4mm x l4.4mm low power consumption C led pulse width control C low shut down current C external led drive-current control shutdown current 1ua max supply voltage : 2.4 v to 3.6 v typical detection distance 30mm based on kodak 18% grey card arti?cial light immunity operational in sunlight conditions analog & digital output available C built in hysteresis comparator for digital output led stuck hi protection applications pda and mobile phones portable and handheld devices personal computers/notebooks contactless switches ordering information part number package type shipping option APDS-9120-020 tape & reel 2500
2 absolute maximum ratings (ta=25c) parameter symbol min. max. units conditions supply voltage v cc 0 4.0 v peak led current iledpk 0 500 ma pulsed at 12.5% duty-cycle re?ow soldering temperature 260 c input logic voltage vi 0 4.0 v recommended operating conditions parameter symbol min. max. units conditions operating temperature t a -40 85 c storage temperature t s -40 100 c supply voltage v cc 2.4 3.6 v electrical & optical speci?cations (ta=25c) parameters symbol min. typ. max. units conditions input logic high voltage, ledon v ih 1.6 C v cc v logic high voltage, enb v ih 1.4 C v cc v for v cc = 2.4v 1.5 C v cc v for 2.4 < v cc 3v 1.7 C v cc v for 3 < v cc 3.6v logic low voltage, ledon v il 0 C 0.3 v logic low voltage, enb v il 0 C 0.3 v logic high input current, ledon i ih C 0.1 1 ua v i v ih logic high input current, enb i ih C 0.1 1 a v i v ih logic low input current, ledon i il C 0.1 1 a v i v il logic low input current, enb i il C 0.1 1 a v i v il shutdown current i sd C 0.3 1 ua v cc = 3v, enb = 3v idle current i cc C 500 650 a v cc = 3v, enb = 0v output analog output v pfilt 1.25 1.9 2.55 v v cc = 3v, enb = 0v, ledon = 10 khz, 50% dc, continuous pulses; r3 = 1mohm, c3 = 3.3nf; kodak 18% grey card at detectable distance = 10mm from the apds- 9120 digital output v ol 0 C 0.3 v i dout(low) = 2ma, v cc = 3v rise time(dout) t r C1Cus v cc = 3v, r2 = 10k , frequency = 10khz fall time(dout) t f C1Cus v cc = 3v, r2 = 10k , frequency = 10khz transmitter max i led pulse width max-pw C 120 C s v cc = 3v, enb = 0v i led peak pulse current iledpk 85 120 155 ma v cc = 3v, r1 = 10 hysterisis comparator hysterisis v hys C 40 C mv v cc = 3v threshold voltage v th C 655 C mv v cc = 3v ambient light tolerance 100k - iux sun light 10k - incandescent 5k - fluorescent 10k - halogen
3 apds-9120 internal block diagram v-i converter c3 led driver with stuck high protection sunlight cancellation tia (4) vcc (7) enbar (5) ledon (10) gnd (9) dout (6) ledk (1) pfilt r1 r2 vio led pin r3 (3) nc3 (8) nc8 (2) nc2 comparator apds-9120 i/o pins con?guration table pin symbol type description 1 pfilt analog o/p analog output connect to integration circuit (r3 & c3) 2 nc2 C no connection 3 nc3 C no connection 4v cc supply voltage supply 5 ledon digital i/p led driver input leda will turn o? when ledon is stuck in high state for more than max-pw 6 ledk led cathode connect to a current limiting resistor 7 enbar digital i/p power down enable enb = 0 normal mode operation enb = 1 shut down mode 8 nc8 C no connection 9 dout digital o/p digital output an open drain output that requires a pull-up resistor of recommended value 10k dout = 0 when vpfilt > vth dout = v cc when vpfilt < vth 10 gnd ground ground 1 2 3 45 6 7 8 9 10
4 led spectal response 0.00 0.20 0.40 0.60 0.80 1.00 700 800 900 1000 1100 1200 wavelength in nm relative response rel icc vs vcc 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc rel icc rel icc vs vcc avg isd vs temp 000.0e+0 50.0e-9 100.0e-9 150.0e-9 200.0e-9 250.0e-9 300.0e-9 350.0e-9 400.0e-9 -40 -20 0 20 40 60 80 100 tem p in de g rees avg isd detector spectral response 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 600 700 800 900 1000 1100 wavelength in nm rel response avg rel icc vs temp at vcc=3v 0.9 0.92 0.94 0.96 0.98 1 1.02 -40 -20 0 20 40 60 80 100 temp in degress avg rel icc rel pfilt vs vcc 0 0.2 0.4 0.6 0.8 1 1.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc rel pflt avg rel icc vs temp at vcc=3v avg isd vs temp rel pfilt vs vcc typical characteristics figure 1. led emitting spectrum figure 2. pin spectral sensitivity figure 3. relative supply current over supply voltage figur e 4. average relative supply current over temperature figure 5. average shutdown current over temperature figure 6. relative output pfilt over supply voltage
5 figure 7. average relative output pfilt over temperatur e figure 8. relative iled current over temperature figure 9. relative output pfilt over detection distance figure 10. angular response angular response avg rel pfilt vs temp at 3v 0 0.2 0.4 0.6 0.8 1 1.2 -40 -20 0 20 40 60 80 100 temp in degrees avg rel pflt rel iled vs vcc 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc rel iled rel pfilt vs distance 0 0.2 0.4 0.6 0.8 1 1.2 0102030405060 distance in mm rel pflt angular response 0 0.2 0.4 0.6 0.8 1 -90 -70 -50 -30 -10 10 30 50 70 90 an g le in de g rees rel response avg rel pfilt vs temp at 3v rel iled vs vcc rel pfilt vs distance
6 2.11 0.18 1.17 1.02 1 2 3 45 6 7 8 9 10 led detector 0.20 0.05 0.05 1.10 1 1.20 1.20 4.4 4.4 0.30 0.05 0.90 0.48 0.95 0.70 1.50 1.05 0.70 1.06 0.75 1.20 0.8 1 1.20 1.20 r0.15 0.05 1.2 0.8 yww laser groove apds-9120 package dimensions top view side view pin 1 : pfilt pin 2 : nc2 pin 3 : nc3 pin 4 : vcc pin 5 : ledon pin 6 : ledk pin 7 : enbar pin 8 : nc8 pin 9 : dout pin 10 : gnd bottom view notes: 1. all dimensions are in millimeters. dimension tolerance is 0.1 mm unless otherwise stated. 2. this package contains no lead. 3. do not connect the bottom exposed pads. 4. no pcb circuitry under the device. marking details font type : stroke roman font size : 0.3mm marking type : laser format : yww y = year (last digit) ww = week number (two digits)
7 tape and reel dimensions 9 9 max 4.68 0.10 4.680.10 0.28 0.02 0.138 0.10 dimensions in mm ? 1.00 0.25 5.50 0.05 1.75 0.10 2.00 0.05 4.00 0.10 8.00 0.10 ? 1.50 0.10 12.0 0.30 C0.10 reel drawings
8 process zone symbol t maximum t/ time or duration heat up p1, r1 25c to 150c 3c/s solder paste dry p2, r2 150c to 200c 100s to 180s solder re?ow p3, r3 p3, r4 200c to 260c 260c to 200c 3c/s -6c/s cool down p4, r5 200c to 25c -6c/s time maintained above liquidus point, 217c > 217c 60s to 120s peak temperature 260c C time within 5c of actual peak temperature C 20s to 40s time 25c to peak temperature 25c to 260c 8mins recommended re?ow pro?le 50 100 300 150 200 250 t-time (seconds) 25 80 120 150 180 200 230 255 0 t - temperature (c) r1 r2 r3 r4 r5 217 max 260c 60 sec to 90 sec above 217 c p1 heat up p2 solder paste dry p3 solder reflow p4 cool down the re?ow pro?le is a straight-line representation of a nominal temperature pro?le for a convective re?ow solder process. the temperature pro?le is divided into four process zones, each with di?erent t/ time tem- perature change rates or duration. the t/ time rates or duration are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and component pins are heated to a temperature of 150c to activate the ?ux in the solder paste. the temperature ramp up rate, r1, is limited to 3c per second to allow for even heating of both the pc board and component pins. process zone p2 should be of su?cient time duration (100 to 180 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder. process zone p3 is the solder re?ow zone. in zone p3, the tem- perature is quickly raised above the liquidus point of solder to 260c (500f) for optimum results. the dwell time above the liquidus point of solder should be between 60 and 90 seconds. this is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. beyond the recommended dwell time the in- termetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreli- able connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25c (77f) should not exceed 6c per second maximum. this limitation is necessary to allow the pc board and component pins to change dimensions evenly, putting minimal stresses on the component. it is recommended to perform re?ow soldering no more than twice.
9 smt assembly application note 1.1 solder pad, mask and metal stencil aperture 1.2 recommended land pattern figure 11. stencil and pcba figure 12. recommended land pattern metal stencil for solder paste printing stencil aperture solder mask land pattern pcba notes: 1. do not connect the nc (no connect) pins. 2. manual soldering on apds-9120 is not recommended. please refer to recommended re?ow pro?le for soldering. 4.7 4.4 unit: mm tolerance: 0.1mm land pattern 4.7 4.4 1.2 1.2 1.0 1.15 0.4 1.20 0.8 0.9 r 0.2
10 1.3 recommended metal solder stencil aperture it is recommended that a 0.11 mm thick stencil be used for solder paste printing. aperture opening for shield pad is 0.8mm x 0.4mm (as per land pattern). this is to ensure adequate printed solder paste volume and no shorting. figure 13. solder stencil aperture figure 14. adjacent land keepout and solder mask areas 1.4 adjacent land keepout and solder mask areas adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. there should be no other smd components within this area. the minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. note: wet/liquid photo-imageable solder resist/mask is recommended. 0.11 4.7 4.7 unit: mm aperture opening 5.7 mm 5.7 mm solder mask area min. 0.2 mm
11 recommended pickup nozzle dimension in mm top view side view bottom view
12 apds-9120 typical timing waveforms note: pulses at ledon can only be activated at least 20us after enb turn from high to low. burst pulses >50ns v cc enb ledon pflit dout >20 s v th
13 typical application circuit r3 gnd dou t enbar ledon v cc nc3 p fi l t nc2 nc8 ledk vcc v i 0 c 1 c2 c3 r 1 r2 5 4 2 3 1 1 0 9 8 7 6 apds - 9 1 20 mcu note: 1. do not connect the nc (no connect) pins
14 recommended operating condition (a) recommended burst pulse to drive ledon (pin5) : pulsing waveform 50 us time with pulsing = period x number of pulses = 5 ms interval time between burst pulses = 1s r1 10 ohm iled (typ) 120ma number of burst pulse 50 period of burst pulse 100us duty cycle of burst pulse 50% interval between burst pulse 1 sec (b) recommended components used: component recommended values r1 10 ohm r2 10k ohm r3 1m ohm c1 100nf, ceramic c2 6.8uf, tantalum c3 3.3nf, ceramic note: 1. r3 and c3 are integrated circuit that can be adjusted to meet desired detectable distance 2. detectable distance is the distance when the object is ?rst detected to trigger a low at dout (pin9).
15 apds-9120 host device cover or substrate of touch panel light guide at emitter: width or diameter = 1.2mm, length < 5mm light guide at detector: width or diameter = 1.3mm, length < 5mm transparent thin layer or ito thin ?lm, < 0.5mm thickness opaque ba?e figure a1. recommended window design (side view) appendix a1: window and light guide design guide to ensure that the performance of the apds-9120 will not be a?ected by improper window design, there are some criteria requested on the dimensions and design of the window. it is recommended that two separate light guides being put on top of apds-9120, one for the emitter and one for the photodiode to reduce the crosstalk level between the emitter and detector. take note that the light guide centers must coincide with the holes opening at the emitter and the photodiode of apds-9120. to have better perfor- mance, an opaque ba?e is suggested to add in between the two light guides. a typical con?guration of light guide is shown below, fig. a1. both rectangular and round shape light guide can be used. the width of rectangular or diameter of round light guide is recommended as 1.2 mm for emitter side, and 1.3mm for detector side. the light guide can have a latch structure for mounting purpose. the length of light guide is recommended to be less than 5mm. a thin transparent layer can also be added on the cover, for cosmetic purpose. this layer can be the ito thin ?lm also for resistive touch panel purpose. it is recommended that this layer to be <0.5mm. adding the light guide and window, the detected signal at a given led driving setting will be reduced, the value of which will be dependant to the light guide dimensions and con?gurations, as well as the transparency of the materials. it is recommended to use high transparency epoxy (t>85%), for example, ge 121r for the light guide. transparent thin layer or ito thin ?lm, < 0.5mm thickness opaque ba?e apds-9120 light guide at emitter host device cover or substrate light guide at detector figure a2. 3-d view of apds-9120
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. av02-1937en - november 24, 2009

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